Here's why Taiwan can't do it: TSMC being nothing but a fab is actually a downside in the sense that engineers will only design chips that make use of existing technology. If Taiwan is doing EUV, engineers design for that. But no one is asking Taiwan to do backside power delivery, so Taiwan has no incentive to develop that in-house capability in the first place.

(http://www.autoadmit.com/thread.php?thread_id=5650097&forum_id=2E#48452781)

Fab Cost, SRAM Scaling, WFE Implications, Backside Power Details, TSMC, Samsung, Intel, Rapidus

TSMC won FinFET. All noteworthy leading edge logic designs, even Intel’s, are manufactured on TSMC’s N5 and N3 process in southern Taiwan. Competitors have been left in the dust. Samsung has had poor performance and poor yields since their 7nm, Intel is still early in its journey to recovery with Intel 4 and 3; neither have major external or internal customers ordering on these nodes in volume.

Future dominance is not guaranteed for TSMC. FinFETs, cannot scale further and SRAM shrink has been dead for a few nodes. The industry is at a crucial inflection point. Leading-edge logic must adopt two new paradigms in the next 2-3 years: gate all around (GAA) and backside power delivery (BSPDN or backside power delivery network).

Intel fell apart with their 10nm node and lost their 3 year lead for a number of reasons including not adopting EUV and transitioning to cobalt metallization with an immature tool supply chain despite warnings from Applied Material that their tools were not ready. The new paradigms of GAA and BSPDN present new opportunities in the foundry pecking order. They could even potentially open the door to a new entrant to the space – Rapidus, the Japanese government backed 2nm foundry startup.

As the capital expenditures needed to build leading edge fabs skyrockets, this means either Samsung or Intel could be forced to drop out of the race. Below we’ll discuss these topics in detail: a deep dive into BSPDN tech followed by leading edge logic roadmaps from all four foundries, competitiveness of their process technologies, SRAM scaling, and our model of 2nm capex and wafer fab equipment (WFE) spend.

Gate All Around is not new. According to Samsung it has been in high volume production for a couple years, but the reality is that this is only in a single low volume bitcoin mining chip that doesn’t have any SRAM and a <20mm^2 watch chip. The gate all around architecture is important topic given that all leading-edge nodes will use it from 2nm through the end of the decade. We’ve covered the transistor change in these two previous reports, these are a great starting place if you need a refresher:"

https://semianalysis.com/2024/10/01/clash-of-the-foundries/

(http://www.autoadmit.com/thread.php?thread_id=5650097&forum_id=2E#48452786)

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

FinFETs, cannot scale further

(http://www.autoadmit.com/thread.php?thread_id=5650097&forum_id=2E#48452791)

https://markets.financialcontent.com/stocks/article/tokenring-2026-1-19-the-backside-revolution-how-intels-powervia-architecture-is-solving-the-ai-power-wall

(http://www.autoadmit.com/thread.php?thread_id=5650097&forum_id=2E#49868631)

https://overclock3d.net/news/misc/why-amd-wants-engineers-with-knowledge-of-intel-silicon/

(http://www.autoadmit.com/thread.php?thread_id=5650097&forum_id=2E#49868635)